rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adp3820 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 lithium-ion battery charger functional block diagram v in is gate v out sd 50mv + C bias v ref adp3820 gnd features 6 1% total accuracy 630 m a typical quiescent current shutdown current: 1 m a (typical) stable with 10 m f load capacitor 4.5 v to 15 v input operating range integrated reverse leakage protection 6-lead sot-23-6 and 8-lead so-8 packages programmable charge current C20 8 c to +85 8 c ambient temperature range internal gate-to-source protective clamp applications li-ion battery chargers desktop computers hand-held instruments cellular telephones battery operated devices general description the adp3820 is a precision single cell li-ion battery charge controller that can be used with an external power pmos de- vice to form a two-chip, low cost, low dropout linear battery charger. it is available in two voltage options to accommodate li-ion batteries with coke or graphite anodes. the adp3820s high acc uracy ( 1%) low shutdown current (1 m a) and easy charge current programming make this device especially attrac- tive as a battery charge controller. charge current can be set by an external resistor. for example, 50 m w of resistance can be used to set the charge current to 1 a. additional features of this device include foldback current limit, overload recovery, and a gate-to-source voltage clamp to protect the external mosfet. the proprietary circuit also minimizes the reverse leakage current from the battery if the input voltage of the charger is disconnected. this feature elimi- nates the need for an external serial blocking diode. the adp3820 operates with a wide input voltage range from 4.5 v to 15 v. it is specified over the industrial temperature range of C20 c to +85 c and is available in the ultrasmall 6-lead surface mount sot-23-6 and 8-lead soic packages. c1 10 m f + C r1 10k v v in +5v r s 50m v 22 m f v out li-ion battery i o = 1a ndp6020p gnd is gate v in sd v out adp3820-xx figure 1. li-ion charger application circuit
C2C rev. a adp3820Cspecifications 1 parameter conditions symbol min typ max units input voltage v in 4.5 15 v output voltage accuracy v in = v out + 1 v to 15 v v out C1 +1 % v sd = 2 v quiescent current shutdown mode v sd = 0 v i gnd 115 m a normal mode v sd = 2 v i gnd 630 800 m a gate to source clamp voltage 6 10 v gate drive minimum voltage 2 0.7 v gate drive current (sink/source) 1 ma gain d d v v gs out ? ? ? ? 80 db current limit threshold voltage v in C v is 40 75 mv load regulation i out = 10 ma to 1 a, circuit of figure 1 C10 +10 mv line regulation v in = v out + 1 v to 15 v i out = 0.1 a circuit of figure 1 (no battery) C10 +10 mv sd input voltage v ih v sd 2.0 v v il 0.4 v sd input current v sd = 0 v to 5 v i sd C15 +15 m a output reverse leakage current v in = floating i disch 35 m a notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 provided gate-to-source clamp voltage is not exceeded. specifications subject to change without notice. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3820 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings* input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 20 v enable input voltage . . . . . . . . . . . . . . . 0.3 v to (v in + 0.3 v) operating ambient temperature range . . . . C20 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c q ja , so-8 package . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w q ja , sot-23-6 package . . . . . . . . . . . . . . . . . . . . 230 c/w lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220 c esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kv *this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ordering guide voltage package marking model output option* code adp3820art-4.1 4.1 v rt-6 (sot-23-6) bac adp3820art-4.2 4.2 v rt-6 (sot-23-6) bbc adp3820ar-4.1 4.1 v so-8 adp3820ar-4.2 4.2 v so-8 *sot = surface mount package. so = small outline. contact the factory for availability of other output voltage options. (v in = [v out + 1 v] t a = C20 8 c to +85 8 c, unless otherwise noted)
adp3820 C3C rev. a pin function descriptions pin pin sot-23-6 so-8 name function 18 sd shutdown. pulling this pin low will disable the output. 2 7 gnd device ground. this pin should be tied to system ground closest to the load. 35v out output voltage sense. this pin is connected to the mosfets drain and directly to the load for optimal load regulation. bypass to ground with a 10 m f or larger capacitor. 4 3 gate gate drive for the external mosfet. 54v in input voltage. this is also the positive terminal connection of the current sense resistor. 6 1 is current sense. used to sense the input current by monitoring the voltage across the current sense resistor. it is connected to the more negative terminal of the resistor as well as the power mosfets source pin. is pin should be tied to the v in pin if the current limit feature is not used. 2, 6 nc no connect. pin configurations so-8 rt-6 (sot-23-6) top view (not to scale) 8 7 6 5 1 2 3 4 nc = no connect is nc gate v in sd gnd nc v out adp3820 top view (not to scale) 6 5 4 1 2 3 sd gnd v out is v in gate adp3820
adp3820 C4C rev. a Ctypical performance characteristics i load C ma 4.110 4.105 4.090 0 1000 200 output voltage C v 400 600 800 4.100 4.095 v in = 5.1v figure 2. v out vs. i load (v in = 5.1 v)* 4.110 4.105 4.090 515 7 output voltage C v 91113 4.100 4.095 input voltage C v i load = 1a figure 3. v out vs. v in (i load = 1 a)* 4.110 4.105 4.090 515 7 output voltage C v 91113 4.100 4.095 input voltage C v i load = 10ma figure 4. v out vs. v in (i load = 10 ma)* input voltage C v 0.760 0.740 0.680 515 7 i gnd C ma 91113 0.720 0.700 0.660 0.640 0.620 i load = 10ma figure 5. i gnd vs. v in (i load = 10 ma)* input voltage C v 0.900 0.850 0.700 515 7 i gnd C ma 11 13 0.800 0.750 i load = 1a 9 figure 6. i gnd vs. v in (i load = 1 a)* i load C ma 1.200 0.500 0.001 1000 i gnd C ma 1.100 10 0.1 1.000 0.900 0.800 0.700 0.600 v in = 5.1v figure 7. i gnd vs. i load (v in = 5.1 v)* * reference figure 1.
adp3820 C5C rev. a temperature C 8 c 1.100 0.500 C40 80 C20 i gnd C ma 0 20 40 60 1.000 0.900 0.800 0.700 0.600 v in = 5.1v i load = 10ma figure 8. quiescent current vs. temperature* input voltage C v 00 123454 321 4.5 4.0 0 output voltage C v 2.0 1.5 1.0 0.5 3.0 2.5 3.5 i load = 10ma figure 9. power-up/power-down* 4.2 4.1 4.0 5.5 7.0 i load = 10ma c out = 10 m f output voltage C v input voltage C v figure 10. line transient response (10 m f output cap)* temperature C 8 c 4.230 4.110 C40 80 C20 output voltage C v 0 20 40 60 4.210 4.190 4.170 4.150 4.130 4.090 4.070 v out = 4.2v v out = 4.1v figure 11. v out vs. temperature, v in = 5.1 v, i load = 10 ma* frequency C hz 0 C100 10 1m psrr C db C50 100 1k 10k 100k C10 C20 C30 C40 C60 C70 C80 C90 10m c load = 10 m f i load = 1ma figure 12. ripple rejection* i load C ma 5.000 4.000 0.000 0 140 20 output voltage C v 40 60 80 100 120 3.000 2.000 v in = 5.1v r s = 0.5 v 1.000 figure 13. current limit foldback*
adp3820 C6C rev. a application information the adp3820 is very easy to use. a p-channel power mos- fet and a small capacitor on the output is all that is needed to form an inexpensive li-ion battery charger. the advantage of using the adp3820 controller is that it can directly drive a pmos fet to provide a regulated output current until the battery is charged. when the specified battery voltage is reached, the charge current is reduced and the adp3820 maintains the maximum specified battery voltage accurately. when fully charged, the circuit in figure 1 works like a well known linear regulator, holding the output voltage within the specified accuracy as needed by single cell li-ion batteries. the output is sensed by the v out pin. when charging a discharged battery, the circuit maintains a set charging current determined by the current sense resistor until the battery is fully charged, then reduces it to a trickle charge to keep the battery at the specified voltage. the voltage drop across the r s current sense resistor is sensed by the is input of the adp3820. at minimum battery voltage or at shorted battery, the circuit reduces this current (foldback) to limit the dissipation of the fet (see fig- ure 13). both the v in input and v out sense pins of the ic need to be bypassed by a suitable bypass capacitor. a 6 v gate-to-source voltage clamp is provided by the ad p3820 to protect the mosfet gates at higher source voltages. the adp3820 also has a ttl sd input, which may be connected to the input voltage to enable the ic. pulling it to low or to ground will disable the fet-drive. design approach due to the lower efficiency of linear regulator charging, the most important factor is the thermal design and cost, which is the direct function of the input voltage, output current and thermal impedance between the mosfet and the ambient cooling air. the worse-case situation is when the battery is shorted since the mosfet has to dissipate the maximum power. a tradeoff must be made between the charge current, cost and thermal requirements of the charger. higher current requires a larger fet with more effective heat dissipation leading to a more expensive design. lowering the charge current reduces cost by lowering the size of the fet, possibly allowing a smaller package such as sot-23-6. the following designs consider both options. furthermore, each design is evaluated under two input source voltage conditions. regarding input voltage, there are two options: a. the input voltage is preregulated, e.g., 5 v 10% b. the input voltage is not a preregulated source, e.g., a wall plug-in transformer with a rectifier and capacitive filter. higher current option a. preregulated input voltage (5 v 6 10%) for the circuit shown in figure 1, the required q ja thermal impedance can be calculated as follows: if the fet data sheet allows a max fet junction temperature of t jmax = 150 c , then at 50 c ambient and at convection cooling, the maximum al- lowed d t junction temperature rise is thus, t jmax C t amax = 150 c C 50 c = 100 c. the maximum current for a shorted or discharged battery is reduced from the set charge current by a multiplier factor shown in figure 13 due to the foldback current limiting feature of the adp3820. this k factor between v o of 0 v to about 2.5 v is: k ~ 0.65. q j a = d t/ ( i o k v in ) = 100 / (1 0.65 5) = 30.7 c/w this thermal impedance can be realized using the transistor shown in figure 1 when surface mounted to a 40 40 mm double-sided pcb with many vias around the tab of the surface- mounted fet to the backplane of the pcb. alternatively, a to-220 packaged fet mounted to a heatsink could be used. the q or thermal impedance of a suitable heatsink is calculated below: q < ( q ja C q jc ) = 30.7 C 2 = +28.7 c/w where the q jc , or junction-to-case thermal impedance of the fet can be read from the fet data sheet. a low cost such heatsink is type pf430 made by thermalloy, with a q = +25.3 c/w. the current sense resistor for this application can be simply calculated: r s = v s / i o = 0.05/1 = 50 m w where v s is specified on the data sheet as current limit threshold voltage at 40 mv C75 mv. for battery charging applications, it is adequate to use the typical 50 mv midvalue. b. nonpreregulated input voltage if the input voltage source is, for example, a rectified and capacitor-filtered secondary voltage of a small wall plug-in transformer, the heatsinking requirement is more demanding. the v inmin should be specified 5 v, but at the lowest line volt- age and full load current. the required thermal impedance can be calculated the same way as above, but here we have to use the maximum output rectified voltage, which can be substan- tially higher than 5 v, depending on transformer regulation and line voltage variation. for example, if v inmax is 10 v q ja = d t/ ( i o k v inmax ) = 100 / (1 0.65 10) = +15.3 c/w the q suitable heatsink thermal impedance: q < q ja C q jc = 15.3 C 2 = 13.3 c/w a low cost heatsink is type 6030b made by thermalloy, with a q = +12.5 c/w. lower current option a. preregulated input voltage (5 v 6 10%) if lower charging current is allowed, the q ja value can be increased, and the system cost decreased. the lower cost is assured by using an inexpensive mosfet with, for example, a ndt452p in a sot-23-6 package mounted on a small 40 40 mm area on double-sided pcb. this provides a convection cooled ther- mal impedance of q ja = +55 c/w, presuming many vias are used around the fet to the backplane. allowing a maximum fet junction temperature of +150 c, at +50 c ambient, and at convection cooling the maximum allowed heat rise is thus 150 cC50 c = 100 c. the maximum foldback current allowed: i fb = d t/ ( q v in ) = 100 / (55 5) = 0.33 a thus the full charging current: i outmax = i fb / k = 0.5 a k is calculated in the above example.
adp3820 C7C rev. a the current sense resistor for this application: r s = v s /i o = 0.05/0.5 = 100 m w fet selection the type and size of the pass transistor are determined by the threshold voltage, input-output voltage differential and load current. the selected pmos must satisfy the physical and ther- mal design requirements. to ensure that the maximum v gs provided by the controller will turn on the fet at worst case conditions, (i.e., temperature and manufacturing tolerances) the maximum available v gs must be determined. maximum v gs is calculated as follows: v gs = v in C v be C i outmax r s where i outmax = maximum output current r s = current sense resistor v be ~ 0.7 v (room temperature) ~ 0.5 v (hot) ~ 0.9 v (cold) for example: v in = 5 v, and i outmax = 1 a, v gs = 5 v C 0.7 v C 1 a 50 m w = 4.25 v if v gs < 5 v, logic level fet should be considered. if v gs > 5 v, either logic level or standard mosfet can be used. the difference between v in and v o (v ds ) must exceed the voltage drop due to the sense resistor plus the on-resistance of the fet at the maximum charge current. the selected mosfet must satisfy these criteria; otherwise, a different pass device should be used. v ds = v in C v o = 5 v C 4.2 v = 0.8 v the maximum r ds(on) required at the available gate drive (v dr ) and drain-to-source voltage (v ds ) is: r ds ( on ) = v ds / i outmax from the drain-to source current vs. drain-to-source voltage vs. gate drive graph off the mosfet data sheet, it can be de- termined if the above calculated r ds(on) is higher than the graph indicates. however, the value read from the mosfet data sheet graph must be adjusted based on the junction temperature of the mosfet. this adjustment factor can be obtained from the normalized r ds(on) vs. junction temperature graph in the mosfet data sheet. external capacitors the adp3820 is stable with or without a battery load, and virtually any good quality output filter capacitors can be used (anycap?), independent of the capacitors minimum esr (effective series resistance) value. the actual value of the capacitor and its associated esr depends on the g m and capaci- tance of the external pmos device. a 10 m f tantalum or alumi- num electrolytic capacitor at the output is sufficient to ensure stability for up to a 10 a output current. shutdown mode applying a ttl high signal to the sd pin or tying it to the input pin will enable the output. pulling this pin low or tying it to ground will disable the output. in shutdown mode, the controllers quiescent current is reduced to less than 1 m a. gate-to-source clamp a 6 v gate-to-source voltage clamp is provided by the adp3820 to protect most mosfet gates in the event the v in > v gs allowed and the output is suddenly shorted to ground. this allows use of the new, low r ds(on) mosfets. short circuit protection the power fet is protected during short circuit conditions with a foldback type of current limiting that significantly re- duces the current. see figure 13 for foldback current limit information. current sense resistor current limit is achieved by setting an appropriate current sense resistor (r s ) across the current limit threshold voltage. current limit sense resistor, r s , is calculated as shown above. proper derating is advised to select the power dissipation rating of the resistor. the simplest and cheapest sense resistor for high current appli- cations, (i.e., figure 1) is a pcb trace. however, the tempera- ture dependence of the copper trace and the thickness tolerances of the trace must be considered in the design. the resistivity of copper has a positive temperature coefficient of +0.39%/ c. coppers tempco, in conjunction with the proportional-to- absolute temperature ( 0.3%) current limit voltage, can provide an accurate current limit. table i provides the typical resistance values for pcb copper traces. alternately, an appropriate sense resistor, such as surface mount sense resistors, available from krl, can be used. table i. printed circuit copper resistance conductor conductor resistance thickness width/inch m v /in 1/2oz/ft 2 (18 m m) 0.025 39.3 0.050 19.7 0.100 9.83 0.200 4.91 0.500 1.97 1oz/ft 2 (35 m m) 0.025 19.7 0.050 9.83 0.100 4.91 0.200 2.46 0.500 0.98 2oz/ft 2 (70 m m) 0.025 9.83 0.050 4.91 0.100 2.46 0.200 1.23 0.500 0.49 3oz/ft 2 (106 m m) 0.025 6.5 0.050 3.25 0.100 1.63 0.200 0.81 0.500 0.325 anycap is a trademark of analog devices, inc.
adp3820 C8C rev. a c2986aC2C9/99 printed in u.s.a. 6-lead plastic surface mount package rt-6 (sot-23-6) 0.122 (3.10) 0.106 (2.70) pin 1 0.118 (3.00) 0.098 (2.50) 0.075 (1.90) bsc 0.037 (0.95) bsc 1 3 4 5 6 2 0.071 (1.80) 0.059 (1.50) 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 8 0 8 0.020 (0.50) 0.010 (0.25) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) 8-lead narrow body package so-8 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 8 0 8 0.0196 (0.50) 0.0099 (0.25) 3 45 8 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) pcb layout issues for optimum voltage regulation, place the load as close as pos- sible to the devices v out and gnd pins. it is recommended to use dedicated pcb traces to connect the mosfets drain to the positive terminal and gnd to the negative terminal of the load to avoid voltage drops along the high current carrying pcb traces. outline dimensions dimensions shown in inches and (mm). if pcb layout is used as heatsink, adding many vias around the power fet helps conduct more heat from the fet to the back- plane of the pcb, thus reducing the maximum fet junction temperature.
package/price information 1% precision, single cell li - ion battery charger * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit in the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability for further information. model status package description pin count temperature range price* (100 - 499) adp3820ar - 4.1 production std s.o. pkg (soic) 8 industrial $1.04 adp3820ar - 4.1 - reel production std s.o. pkg (soic) 8 industrial - adp3820ar - 4.2 production std s.o. pkg (soic) 8 industrial $1.04 adp3820ar - 4.2 - reel production std s.o. pkg (soic) 8 industrial - adp3820art - 4.1 - rl production sot - 23, sot - 143 or sot - 223 6 industrial - adp3820art-4.1-rl7 production sot-23, sot-143 or sot-223 6 industrial - adp3820art-4.2-rl production sot-23, sot-143 or sot-223 6 industrial - adp3820art-4.2-rl7 production sot-23, sot-143 or sot-223 6 industrial -
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